Disturb and its Mitigation in Ferroelectric Field-Effect Transistors With Large Memory Window for NAND Flash Applications

Abstract

We study the disturb characteristics of ferroelectric field-effect transistors (FEFETs) with band-engineered gate stacks. We demonstrate that integrating a dielectric Al2O3 layer within the ferroelectric (FE) Hf<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{0}.{5}}$ </tex-math></inline-formula>Zr<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{0}.{5}}$ </tex-math></inline-formula>O2 layer in the gate stack significantly enhances the memory window (MW), achieving levels suitable for quad-level cell operation (approximately 7.5 V) while operating at a reduced write voltage (below 15 V). Despite these improvements, the band-engineered FEFET exhibits similar pass disturb characteristics in the PGM state as a standard FEFET with an FE-only gate stack. To improve the disturb characteristics, we introduce and validate a periodic refresh-based disturb mitigation scheme, analogous to strategies employed in SSD controllers and flash memory managers for traditional charge trap flash-based NAND chips. This mitigation scheme reduces disturb in the PGM state from ~28% to approximately ~4% in the band-engineered FEFETs, enabling large memory window, low-disturb operation.