IEEE Journal of Solid-State Circuits · 2023 · 21 citations · 49 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureHardware-software Co-designLow-power DesignEmbedded Memory BlocksEnergy-efficient Embedded SystemsHardware AccelerationLow-power Digital Circuit DesignMemory Subsystem DesignPower ManagementEmbedded Hardware Co-designEnergy ConsumptionEnergy-efficient Memory DesignHardware-software Co-optimizationMemory Circuit DesignMultiply-accumulate UnitsReadoutStatic Random-access Memory Design
This article presents a novel static random access memory computing-in-memory (SRAM-CIM) structure designed for high-precision multiply-and-accumulate (MAC) operations with high energy efficiency (EF), high readout accuracy, and short compute latency. The proposed device employs 1) a time-domain incremental-accumulation (TDIA) scheme to enable high-accumulation MAC operations while maintaining a large signal margin across MAC values (MACVs), 2) a dynamic differential-reference (D2REF) scheme based on software-hardware co-design to reduce read energy consumption, and 3) a low-dMACV-aware recursive time-to-digital converter (LMAR-TDC) for implementation with the D2REF scheme to further suppress readout energy consumption. A 28 nm 1 Mb SRAM-CIM macro fabricated using foundry-provided compact 6T-SRAM cells achieved EF of 39.31 TOPS/W and compute latency of 6.6 ns for 8b-MAC operations with 64 accumulations per cycle and near-full output precision (22b).
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