A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory

TLDR

Conventional BCAM/TCAM use large 10T/16T cells, much bigger than standard 6T SRAM cells. The paper proposes a BCAM/TCAM that uses standard push‑rule 6T SRAM cells, shrinking array area by 2–5× and enabling reconfiguration as a CAM. It implements a push‑rule 6T SRAM bit cell that supports both storage and CAM functionality, allowing the array to be reconfigured between modes. The 28 nm 6T FDSOI implementation achieves 370 MHz at 1 V with 0.6 fJ/search/bit, supports 787 MHz logical AND/NOR between 64‑bit words, and overall reduces chip area, capacitance, and energy per search while enabling in‑memory computation.

Abstract

Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search operations. In addition, the configurable memory can perform bit-wise logical operations: "AND" and "NOR" on two or more words stored within the array. Thus, the configurable memory with CAM and logical function capability can be used to off-load specific computational operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A logical operation between two 64 bit words achieves 787 MHz at 1 V.