Vertical Channel Transistor (VCT) as Access Transistor for Future 4F² DRAM Architecture

Abstract

In this work, a novel 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> VCT (vertical channel transistor) targeting for next generation of DRAM is proposed. We approached process feasibility and device performance of $\mathbf{4 F}^{2}$ VCT by TCAD simulation. Detailed processes such as BL (bit line) and WL (word line) loop have also been discussed to achieve lx node VCT DRAM. For the first time, silicon demonstration for $8\mathrm{~Gb}$ full array VCT with density as high as $198\ \mathrm{Mbit}/\mathrm{mm}^{2}$ is successfully realized. Besides, we also demonstrated standard switching behavior of VCT access transistor with reasonable device performance.