Fabrication of a Hole‐Type Vertical Resistive‐Switching Random‐Access Array and Intercell Interference Induced by Lateral Charge Spreading

Abstract

Abstract A hole‐type vertical structure is adopted to fabricate a vertically stacked resistive switching random access memory (ReRAM) array. The vertical configuration is more advantageous in lowering the process cost and increasing integration density than the horizontal configuration. However, the memory cells constituting the hole‐type vertical‐ReRAM (V‐ReRAM) array can be short‐circuited if a middle electrode is introduced to stack a rectifying element onto the memory layer. Thus, a self‐rectifying Pt/Ta 2 O 5 /Al‐doped HfO 2 /TiN ReRAM is adopted in this study to prevent the sneak‐current and short‐circuit issues for efficient operation in vertical crossbar array configuration. A two‐ or three‐layer stacked V‐ReRAM is fabricated, and its electrical characteristics are evaluated. High switching uniformity and sufficiently large memory window and rectification ratio are acquired. The low operation power and high switching uniformity render this V‐ReRAM array suitable for high‐capacity storage devices. However, the on‐state data retention needs improvement. Detailed investigation of the three‐layer stacked device identifies that lateral charge spreading between neighboring cells in the V‐ReRAM causes such a problem, which can be mitigated by increasing the intercell distance.