Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with Record-high G_m,max of 559 µS/µm at V_DS=1 V, Record-low DIBL of 10 mV/V and Nearly Ideal SS of 63 mV/dec

Abstract

We experimentally prove that amorphous IGZO FET can be scaled down by connected dual-gate design with enhanced electrostatic control. By connected dual-gate operation and scaled dual stacks, the short channel device (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</inf> =30 nm) achieves near ideal SS of 63 mV/dec and ultra-high on-state current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> ) of 615 µA/µm at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</inf> -V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> =2 V&V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> =1 V. By this design, record-high transconductance (G <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> ) of 559 µS/µm at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> =1 V and record-low drain-induced-barrier-lowering (DIBL) of 10 mV/V are achieved, to our best knowledge, among all the a-IGZO transistors with sub-100 nm channel length reported so far.