An improved method for RTL synthesis with testability tradeoffs

Abstract

A method for high level synthesis with testability is presented with the objective to generate self-testable RTL datapath structures. We base our approach on a new improved testability model that generates various testable design styles while reducing the circuit sequential depth from controllable to observable registers. We follow the allocation method with an automatic test point selection algorithm and with an interactive tradeoff scheme which trades design area and delay with test quality. The method has been implemented and design comparisons are reported.