Testability-driven Synthesis

Testability-Driven Synthesis is a logic synthesis methodology that belongs to the class of design-for-testability techniques, distinguished by its explicit optimization of circuit structures during synthesis to enhance the ease and effectiveness of fault detection and test generation.

57

Publications

1.7K

Citations

120

Authors

57

Institutions

Publications per year

2017–2026

1

Authors

120

  1. KK
    Kurt Keutzer

    University of California, Berkeley, United States

    4 publications · 137 citations

    4

    h-index

  2. SR
    S.M. Reddy

    University of Iowa, United States

    4 publications · 172 citations

    4

    h-index

  3. CP
    C. Papachristou

    Case Western Reserve University, United States

    4 publications · 222 citations

    4

    h-index

  4. IP
    Irith Pomeranz

    University of Iowa, United States

    3 publications · 52 citations

    3

    h-index

  5. SD
    Srinivas Devadas

    Massachusetts Institute of Technology, United States

    3 publications · 109 citations

    3

    h-index

1–5 of 120

Venues

  1. 7

    h-index

  2. Journal of Electronic Testing

    JETTA · 3 publications · 133 citations

    3

    h-index

  3. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 2 publications · 136 citations

    2

    h-index

  4. IEEE Transactions on Computers

    2 publications · 54 citations

    2

    h-index

  5. IEEE Design & Test of Computers

    2 publications · 47 citations

    2

    h-index

1–5