Testability-driven Synthesis
Testability-Driven Synthesis is a logic synthesis methodology that belongs to the class of design-for-testability techniques, distinguished by its explicit optimization of circuit structures during synthesis to enhance the ease and effectiveness of fault detection and test generation.
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1.7K
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120
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2017–2026
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Easily testable realizations for logic functions
S.M. Reddy · Computer-Aided Design · 1973 · 96 citations
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Case Western Reserve University
Cleveland, United States
5 h-index
11 publications
576 citations
University of Iowa
Iowa City, United States
5 h-index
9 publications
213 citations
Politecnico di Milano
Milan, Italy
3 h-index
10 publications
144 citations
University of Illinois Urbana-Champaign
Urbana, United States
3 h-index
5 publications
91 citations
Princeton University
Princeton, United States
3 h-index
3 publications
80 citations
Politecnico di Torino
Turin, Italy
3 h-index
6 publications
94 citations
University of Wisconsin–Madison
Madison, United States
3 h-index
7 publications
359 citations
Synopsys (United States)
Mountain View, United States
3 h-index
3 publications
118 citations
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7 publications · 188 citations
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JETTA · 3 publications · 133 citations
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TODAES · 2 publications · 136 citations
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2 publications · 54 citations
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2 publications · 47 citations
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