Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) · 2002 · 14 citations · 12 references
EngineeringComputer EngineeringCircuit TheoryDesign OptimizationOptimizationInterconnect ArchitectureInterconnect DesignInterconnect TechnologyLow-noise Circuit DesignNoise PredictionNoise Reduction DesignCrosstalkCrosstalk Noise MitigationInterconnect Layout OptimizationInterconnect ModelingInterconnect NoiseInterconnect OptimizationLayout Techniques For Noise ReductionNoise-aware Layout
This paper presents a much improved, highly accurate yet efficient crosstalk noise model, the 2-/spl pi/ model, and applies it to noise-constrained interconnect optimizations. Compared with previous crosstalk noise models of similar complexity, our 2-/spl pi/ model takes into consideration many key parameters, such as coupling locations (near-driver or near-receiver), and the coarse distributed RC characteristics for victim net. Thus, it is very accurate (less than 6% error on average compared with HSPICE simulations). Moreover, our model provides simple closed-form expressions for both peak noise amplitude and noise width, so it is very useful for noise-aware layout optimizations. In particular we demonstrate its effectiveness in two applications: (i) optimization rule generation for noise reduction using various interconnect optimization techniques, (ii) simultaneous wire spacing to multiple nets for noise constrained interconnect minimization.
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Noise in deep submicron digital design
Kenneth L. Shepard, V. Narayanan · 2002 · 230 citations
Engineering, Computer Engineering, Electrical Engineering +17
Buffer insertion for noise and delay optimization
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay · 1998 · 138 citations · Full text