Stephen T. Quay - Concepedia

Author

Stephen T. Quay

IBM Research - Austin

Also Known As

S. Quay, S. T. Quay, S.T. Quay, Stephen Quay, Stephen T. Quay

Publications

869

Citations

H-Index

Concepts

All Affiliations

IBM Research - Austin IBM (United States)University of Illinois Chicago Texas A&M University Iowa State University

About

Stephen T. Quay is an author at IBM Research - Austin specializing in computer engineering, parallel computing, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	13	17	779
2	Computer Engineering	13	17	779
3	Computer Science	10	11	413
4	Business	1	1	11
5	Natural Sciences	1	1	24

Stephen T. Quay

Publications

847

Citations

H-Index

Page 1

	Year	Citations
Buffer insertion for noise and delay optimization Charles J. Alpert, Anirudh Devgan, Stephen T. Quay EngineeringVlsi DesignDelay OptimizationComputer ArchitectureInterconnection Network Architecture	1998	138
Buffer insertion with accurate gate and interconnect delay computation Charles J. Alpert, Anirudh Devgan, Stephen T. Quay EngineeringVlsi DesignVlsi ArchitectureBuffer InsertionComputer Architecture	1999	121
Buffer insertion for noise and delay optimization Charles J. Alpert, A. Devgan, Stephen T. Quay IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringVlsi DesignDelay OptimizationComputer ArchitectureInterconnection Network Architecture	1999	112
Techniques for Fast Physical Synthesis Charles J. Alpert, S.K. Karandikar, Zhuo Li, Proceedings of the IEEE EngineeringElectronic Design AutomationComputer ArchitectureSystem SynthesisComputer-aided Design	2007	83
Buffered Steiner trees for difficult instances Charles J. Alpert, Miloš Hrkić, Jiang Hu,	2001	57
Interconnect synthesis without wire tapering Charles J. Alpert, A. Devgan, J.P. Fishburn, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Wire TaperingElectrical EngineeringEngineeringAdvanced Packaging (Semiconductors)Vlsi Architecture	2001	46
Steiner tree optimization for buffers, blockages, and bays Charles J. Alpert, Gopal Gandham, Jiang Hu, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Mathematical ProgrammingEngineeringVlsi DesignComputer ArchitectureStructural Optimization	2001	41
Buffer insertion with accurate gate and interconnect delay computation Charles J. Alpert, A. Devgan, Stephen T. Quay Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361) Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignVlsi Architecture	2003	40
Fast interconnect synthesis with layer assignment Zhuo Li, Charles J. Alpert, Shiyan Hu, Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignAdvanced Packaging (Semiconductors)	2008	37
Buffer insertion with adaptive blockage avoidance Jiang Hu, Charles J. Alpert, Stephen T. Quay, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Repeater InsertionEngineeringBuffer InsertionComputer EngineeringComputer Architecture	2003	26

Page 1