Buffer insertion with accurate gate and interconnect delay computation

Abstract

Article Free Access Share on Buffer insertion with accurate gate and interconnect delay computation Authors: Charles J. Alpert IBM Austin Research Laboratory, Austin, TX IBM Austin Research Laboratory, Austin, TXView Profile , Anirudh Devgan IBM Austin Research Laboratory, Austin, TX IBM Austin Research Laboratory, Austin, TXView Profile , Stephen T. Quay IBM Server Group, Austin, TX IBM Server Group, Austin, TXView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 479–484https://doi.org/10.1145/309847.309983Published:01 June 1999Publication History 46citation557DownloadsMetricsTotal Citations46Total Downloads557Last 12 Months38Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF