Noise-aware Layout

Noise-Aware Layout is a VLSI layout methodology that systematically integrates parasitic coupling and signal integrity considerations during physical design to mitigate noise-induced malfunctions in high-density integrated circuits.

Publications

1.6K

Citations

145

Authors

Institutions

Publications per year

2017–2026

Variants

Noise-aware Physical Design

Parents

Very-large-scale Integration Layout

Publications

Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects

G. Anelli, M. Campbell, M. Delmastro et al. · IEEE Transactions on Nuclear Science · 1999 · 370 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

Improved crosstalk modeling for noise constrained interconnect optimization

Jason Cong, David Z. Pan, P.V. Srinivas · 2001 · 135 citations

Engineering, Computer Engineering, Circuit Theory +16

VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using Carbon Nanotube FETs

Nishant Patil, Albert Lin, Jie Zhang et al. · 2009 · 107 citations

Engineering, Computer Engineering, Electrical Engineering +17

Charge redistribution and noise margins in domino CMOS logic

Johannes Pretorius, A. Shubat, C.A.T. Salama · IEEE Transactions on Circuits and Systems · 1986 · 66 citations

Engineering, Computer Engineering, Electrical Engineering +17

Issues in the design of domino logic circuits

P. Srivastava, A. Pua, L.R. Welch · 2002 · 52 citations

Engineering, Computer Engineering, Electrical Engineering +16

1–5 of 45

Authors

145

DZ
David Z. Pan
The University of Texas at Austin, United States
3 publications · 159 citations
3
h-index
SK
Sung Kyu Lim
Georgia Institute of Technology, United States
2 publications · 64 citations
2
h-index
PS
P.V. Srinivas
University of California, Los Angeles, United States
2 publications · 149 citations
2
h-index
MT
Mohammad Tehranipoor
University of Connecticut, United States
1 publications · 22 citations
1
h-index
GZ
Guoan Zhong
Purdue University West Lafayette, United States
1 publications · 46 citations
1
h-index

1–5 of 145

Institutions

1–8 of 59

Venues

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
4 publications · 119 citations
4
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2 publications · 30 citations
2
h-index
IEEE Transactions on Circuits and Systems
2 publications · 96 citations
2
h-index
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)
Conference · 1 publications · 14 citations
1
h-index
Journal of Low Temperature Physics
1 publications · 14 citations
1
h-index

1–5