Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition · 2003 · 47 citations · 20 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureDesign AutomationField-programmable Gate ArraysConfigurable Logic BlocksField-programmable Gate Array ArchitectureFpga ArchitectureHigh-level SynthesisLogic SynthesisTiming AnalysisArea EfficiencyArea-delay OptimizationAutomated Design Space ExplorationConfigurable Logic Block DesignConfigurable Logic Cell DesignLogic Element ArchitectureLogic Element DesignReconfigurable Logic Blocks
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic design space exploration to synthesize hardware for a field programmable gate array (FPGA) which meets the user area and frequency specifications. We present an area estimator which is used to estimate the maximum number of configurable logic blocks (CLBs) consumed by the hardware synthesized for the Xilinx XC4010 from the input MATLAB algorithm. We also present a delay estimator which finds out the delay in the logic elements in the critical path and the delay in the interconnects. The total number of CLBs predicted by us is within 16% of the actual CLB consumption and the synthesized frequency estimated by us is within an error of 13% of the actual frequency after synthesis through Synplify logic synthesis tools and after placement and routing through the XACT tools from Xilinx. Since the estimators proposed by us are fast and accurate enough, they can be used in a high level synthesis framework like ours to perform rapid design space exploration.
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Stream-oriented FPGA computing in the Streams-C high level language
Maya Gokhale, Janice M. Stone, Jeffrey M. Arnold et al. · 2002 · 240 citations
Feuer · IEEE Transactions on Computers · 1982 · 137 citations