Logic Element Architecture
Logic Element Architecture is a fundamental computational unit within a Field-Programmable Gate Array that integrates configurable logic functions, storage elements, and routing interfaces to enable user-defined Boolean operations and sequential behavior through programmable interconnectivity.
187
Publications
8.8K
Citations
698
Authors
219
Institutions
Publications per year
2017–2026
28
187
A Regular Layout for Parallel Adders
Brent, Kung · IEEE Transactions on Computers · 1982 · 1.1K citations
The Stratix II logic and routing architecture
David Lewis, Elias Ahmed, Gregg Baeckler et al. · 2005 · 219 citations
1–5 of 187
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219

University of Toronto
Toronto, Canada
10 h-index
22 publications
1.2K citations
Xilinx (United States)
San Jose, United States
6 h-index
17 publications
512 citations
Intel (United States)
Santa Clara, United States
5 h-index
24 publications
1.3K citations
Nanyang Technological University
Singapore, Singapore
4 h-index
14 publications
291 citations

Imperial College London
London, United Kingdom
3 h-index
6 publications
112 citations

Delft University of Technology
Delft, The Netherlands
3 h-index
10 publications
148 citations
Georgia Institute of Technology
Atlanta, United States
3 h-index
8 publications
476 citations
Nagoya University
Nagoya, Japan
3 h-index
6 publications
354 citations
1–8 of 219
8 publications · 292 citations
8
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5 publications · 224 citations
5
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4 publications · 91 citations
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4 publications · 125 citations
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4 publications · 302 citations
4
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