Area-delay Optimization

Area-Delay Optimization is a design methodology in fine-grained reconfigurable architectures that systematically balances the trade-off between hardware resource utilization (area) and computational latency (delay) to achieve optimal performance efficiency under constrained physical implementation.

370

Publications

13.1K

Citations

809

Authors

288

Institutions

Publications per year

2017–2026

Parents

Fine-grained Reconfigurable Architectures

Publications

370

Low-Power and Area-Efficient Carry Select Adder

B. Ramkumar, Harish M. Kittur · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2011 · 383 citations

Engineering, Computer Engineering, Computer Science +17

Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation

Chung-Ping Chen, Chris Chu, Martin D. F. Wong · 1998 · 243 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +15

Directional and single-driver wires in FPGA interconnect

Guy Lemieux, E. Lee, Marvin Tom et al. · 2005 · 242 citations

Engineering, Computer Engineering, Electrical Engineering +17

A First Step Toward Cost Functions for Quantum-Dot Cellular Automata Designs

Weiqiang Liu, Liang Lü, Máire O׳Neill et al. · IEEE Transactions on Nanotechnology · 2014 · 225 citations

Engineering, Computer Engineering, Computer Science +12

FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic

Pramod Kumar Meher, S. Chandrasekaran, Abbes Amira · IEEE Transactions on Signal Processing · 2008 · 198 citations

Engineering, Computer Engineering, Computer Science +17

1–5 of 370

Authors

809

PK
Pramod Kumar Meher
Nanyang Technological University, Singapore
17 publications · 902 citations
14
h-index
MD
Martin D. F. Wong
University of Illinois Urbana-Champaign, United States
7 publications · 514 citations
7
h-index
VB
Vaughn Betz
University of Toronto, Canada
6 publications · 342 citations
6
h-index
CC
Ching Chuen Jong
Nanyang Technological University, Singapore
6 publications · 128 citations
6
h-index
JR
Jonathan Rose
University of Toronto, Canada
6 publications · 329 citations
6
h-index

1–5 of 809

Institutions

288

1–8 of 288

Venues

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
27 publications · 1.6K citations
21
h-index
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
27 publications · 1.1K citations
20
h-index
IEEE Transactions on Circuits & Systems II Express Briefs
9 publications · 434 citations
10
h-index
IEEE Transactions on Circuits and Systems I Regular Papers
8 publications · 294 citations
8
h-index
IEEE Transactions on Computers
5 publications · 163 citations
5
h-index

1–5