Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism

Abstract

This paper describes a way of testing both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM’s architec-ture, which is dynamically reconfigurable, scalable and flex-ible, is named CAS-BUS and have a central controller. All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port. 1