2003 · 10 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignConfigurable Logic BlocksLeakage Power ReductionLow-power Digital Circuit DesignLow-power Fpga DesignTiming AnalysisConfigurable Logic Block DesignDesign MethodologyGate-level DesignLeakage Current ReductionLeakage PowerLeakage Power OptimizationMtcmos CircuitsSleep Transistor Design
Multi‑threshold CMOS is a popular technique for reducing standby leakage power with low delay overhead, and MTCMOS designs typically use large sleep devices to reduce standby leakage at the block level. We provide a formal examination of sneak leakage paths and a design methodology that enables gate‑level insertion of sleep devices for sequential and combinational circuits. The methodology involves formal analysis of sneak leakage paths and systematic placement of gate‑level sleep FETs in both sequential and combinational logic. A fabricated 0.13 µm dual‑V_T test chip using this methodology implements a low‑power FPGA core with gate‑level sleep FETs, achieving over 8× standby current reduction and up to 2.2× leakage reduction in active CLBs for some configurations.
Multi-threshold CMOS is a popular technique for reducing standby leakage power with low delay overhead. MTCMOS designs typically use large sleep devices to reduce standby leakage at the block level. We provide a formal examination of sneak leakage paths and a design methodology that enables gate-level insertion of sleep devices for sequential and combinational circuits. A fabricated 0.13 /spl mu/m, dual V/sub T/ test chip employs this methodology to implement a low-power FPGA core with gate-level sleep FETs and over 8/spl times/ measured standby current reduction. The methodology allows local sleep regions that reduce leakage in active configurable logic blocks (CLBs) by up to 2.2/spl times/ (measured) for some CLB configurations.