ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) · 2004 · 40 citations · 27 references
EngineeringComputer EngineeringSystems EngineeringSystem-on-chip DesignSystems ArchitectureVlsi DesignChip PackagingDigital Integrated Circuit DesignHardware SpecificationIntegrated Circuit DesignPhysical DesignVery-large-scale Integration Layout2.5D Integration3D Integrated CircuitsLayout TechniquesSystem-on-chip ArchitectureSystem-on-chip IntegrationThree-dimensional Integrated Circuit LayoutVery-large-scale Integration (Vlsi) DesignVlsi Implementation
We investigate a 3D die-stacking based VLSI integration strategy, socalled 2.5D integration, which can potentially overcome many problems stumbling the development of monolithic system-on-chip (SoC). Here, we review available fabrication technologies and testing solutions for the new integration strategy. We also propose a design driven system implementation schema for this new integration strategy. A layout synthesis framework is under development by us to analyze typical "what if" questions and resolve major physical attributes for a 2.5D system according to the design specification and constraints.
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Future system-on-silicon LSI chips
Mitsumasa Koyanagi, H. Kurino, Kang Wook Lee et al. · IEEE Micro · 1998 · 336 citations
Engineering, Computer Engineering, Electrical Engineering +17
Will physical scalability sabotage performance gains?
Douglas J. Matzke · Computer · 1997 · 277 citations
Testing embedded-core-based system chips
Y. Zorian, Erik Jan Marinissen, S. Dey · Computer · 1999 · 208 citations