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EUV lithography for 22nm half pitch and beyond: exploring resolution, LWR, and sensitivity tradeoffs
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2011
Year
EngineeringElectron-beam LithographyMicroscopyEuv LithographyTarget FabricationOptoelectronic DevicesIntegrated CircuitsInternational Technology RoadmapWafer Scale ProcessingBeam LithographyInstrumentationElectronic PackagingNanolithography MethodElectrical EngineeringIntel CorporationPhysicsHigh SensitivitySemiconductor Device FabricationMicroelectronicsPlasma EtchingMicrofabricationApplied PhysicsHalf PitchOptoelectronicsSensitivity Tradeoffs
The International Technology Roadmap for Semiconductors (ITRS) denotes Extreme Ultraviolet (EUV) lithography as a leading technology option for realizing the 22nm half pitch node and beyond. According to recent assessments made at the 2010 EUVL Symposium, the readiness of EUV materials remains one of the top risk items for EUV adoption. The main development issue regarding EUV resists has been how to simultaneously achieve high resolution, high sensitivity, and low line width roughness (LWR). This paper describes our strategy, the current status of EUV materials, and the integrated post-development LWR reduction efforts made at Intel Corporation. Data collected utilizing Intel's Micro- Exposure Tool (MET) is presented in order to examine the feasibility of establishing a resist process that simultaneously exhibits ≤22nm half-pitch (HP) L/S resolution at ≤11.3mJ/cm<sup>2</sup> with ≤3nm LWR.