ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) · 2004 · 22 citations · 11 references
EngineeringComputer EngineeringComputer ScienceAlgorithmsComputer ArchitectureOptimizationBuffer ManagementInterconnect DesignPower OptimizationRoutingTiming AnalysisBuffer InsertionComplexity AnalysisDelay OptimizationDynamic Programming PrinciplesInterconnect Delay OptimizationMergeMultiway MergingTiming-slack Optimization
As gate delays d e e m faster than wire delays for each teehnolagy generation, buffer insertion hecomes a popular method to reduce the interconnecI delay. Several modem huffer insertion algorithms (e.g.. 17.6.151) are based on van Ginneken’s dynamic programming paradigm [141. However, van Ginneken’s original algorithm does not control buffering resources and tends to over-buffering, thereby wasting area and power. It has been a major open prohlem whether it is possible to optimize slack and at the same time minimize the buffer usage. This paper settles this open problem by showing that for arbitrary integer cost functions, the problem is NP-complete. We also extend the prr-buffer slack technique (121 to minimize the buffer cost. This technique can significantly reduce the running time and memory in buffer cost miniminition problem. The experimental results show that our algorithm can speed up the running time up to 17 times and reduces the memory to 1/30 of traditional best know algorithm. Finally, we show how to efficiently deal with multiway merge in buffer insertion.
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Wire segmenting for improved buffer insertion
Charles J. Alpert, Anirudh Devgan · 1997 · 206 citations
Buffer insertion for noise and delay optimization
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay · 1998 · 138 citations · Full text