Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. · 2005 · 18 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignLeakage Power ReductionLow-power Digital Circuit DesignPower ManagementPower OptimizationPower-aware DesignArea-efficient DesignGate LeakageGate Leakage CurrentGate Oxide LeakageLeakage CurrentLeakage Current ModelingLeakage Current ReductionOn-chip Decoupling
In today's power/ground (P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leakage current becomes worse as the gate oxide layer thickness continues to shrink below 20/spl Aring/. As a result, decaps become leaky due to the gate leakage from CMOS devices. In this paper, we take a first look at the leaky decaps in P/G network optimization. We propose a leakage current model for practical decaps and also present a new two-stage leakage-current-aware approach to efficiently optimize P/G networks in a more area efficient way.
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C.‐J. Richard Shi, Dragos Lungeanu, Jyh-Chwen Lee et al. · Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361) · 2003 · 63 citations
Engineering, Computer Engineering, Electrical Engineering +14