On-chip Decoupling
On-Chip Decoupling is an integrated circuit design technique that belongs to the class of power integrity management methods, distinguished by its implementation of localized capacitance elements directly within the semiconductor die to suppress supply voltage fluctuations and minimize noise coupling between analog and digital subsystems.
122
Publications
6K
Citations
439
Authors
93
Institutions
Publications per year
2017–2026
11
Parents
122
1–5 of 122
439
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Korea Advanced Institute of Science and Technology, South Korea
7 publications · 194 citations
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7
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6
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1–5 of 439
93
IBM (United States)
Armonk, United States
11 h-index
48 publications
2.5K citations

University of Rochester
Rochester, United States
11 h-index
19 publications
491 citations
Korea Advanced Institute of Science and Technology
Daejeon, South Korea
8 h-index
40 publications
1.4K citations
Intel (United States)
Santa Clara, United States
7 h-index
30 publications
2.3K citations
Georgia Institute of Technology
Atlanta, United States
7 h-index
17 publications
496 citations
University of California, Riverside
Riverside, United States
6 h-index
12 publications
294 citations
Tsinghua University
Beijing, China
6 h-index
23 publications
588 citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
5 h-index
14 publications
1.8K citations
1–8 of 93
9 publications · 461 citations
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9 publications · 410 citations
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3 publications · 92 citations
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3 publications · 99 citations
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2 publications · 241 citations
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