On-chip Decoupling

On-Chip Decoupling is an integrated circuit design technique that belongs to the class of power integrity management methods, distinguished by its implementation of localized capacitance elements directly within the semiconductor die to suppress supply voltage fluctuations and minimize noise coupling between analog and digital subsystems.

122

Publications

6K

Citations

439

Authors

93

Institutions

Publications per year

2017–2026

11

Authors

439

  1. EG
    Eby G. Friedman

    University of Rochester, United States

    10 publications · 285 citations

    10

    h-index

  2. JK
    Joungho Kim

    Korea Advanced Institute of Science and Technology, South Korea

    7 publications · 194 citations

    7

    h-index

  3. MP
    Mikhail Popovich

    University of Rochester, United States

    7 publications · 191 citations

    7

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  4. SX
    Sheldon X.-D. Tan

    University of California, Riverside, United States

    6 publications · 150 citations

    6

    h-index

  5. YC
    Yici Cai

    Tsinghua University, China

    5 publications · 123 citations

    5

    h-index

1–5 of 439

Venues

  1. IEEE Journal of Solid-State Circuits

    9 publications · 461 citations

    9

    h-index

  2. 9

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  3. IEEE Transactions on Advanced Packaging

    3 publications · 92 citations

    3

    h-index

  4. 3

    h-index

  5. IEEE Transactions on Power Electronics

    2 publications · 241 citations

    2

    h-index

1–5