Impact of Interlayer and Ferroelectric Materials on Charge Trapping During Endurance Fatigue of FeFET With TiN/Hf_<i>x</i>Zr_1-<i>x</i>O₂/Interlayer/Si (MFIS) Gate Structure

Abstract

We study the impact of different interlayers (ILs) and ferroelectric materials on charge trapping during the endurance fatigue of Si ferroelectric field effect transistor (FeFET) with TiN/Hf_<i>x</i>Zr_1-<i>x</i>O₂/ interlayer/Si (MFIS) gate-stack. We have fabricated FeFET devices with different interlayers (SiO₂ or SiON) and Hf_<i>x</i>Zr_1-<i>x</i>O₂ materials (<inline-formula> <tex-math notation="LaTeX">${x} =0.75$ </tex-math></inline-formula>, 0.6, 0.5) and directly extracted the charge trapping during endurance fatigue. We find that: 1) under the same equivalent oxide thickness (EOT) condition, the increase of dielectric constant and interlayer thickness suppresses charge trapping and improves the endurance characteristics; 2) charge trapping effect is experimentally verified to be the origin of endurance fatigue; and 3) as the spontaneous polarization (<inline-formula> <tex-math notation="LaTeX">${P}_{\text {s}}{)}$ </tex-math></inline-formula> of the Hf_<i>x</i>Zr_1-<i>x</i>O₂ decreases from <inline-formula> <tex-math notation="LaTeX">$25.9~ \boldsymbol {\mu } \text{C}$ </tex-math></inline-formula>/cm² (Hf_0.5Zr_0.5O₂) to <inline-formula> <tex-math notation="LaTeX">$20.3~ \boldsymbol {\mu } \text{C}$ </tex-math></inline-formula>/cm² (Hf_0.6Zr_0.4O₂), the charge trapping behavior decreases, resulting in the slow degradation rate of memory window (MW) during program/erase cycling; in addition, when <inline-formula> <tex-math notation="LaTeX">${P}_{\text {s}}$ </tex-math></inline-formula> further decreases to <inline-formula> <tex-math notation="LaTeX">$8.1~ \boldsymbol {\mu }\text{C}$ </tex-math></inline-formula>/cm² (Hf_0.75Zr_0.25O₂), the initial MW nearly disappears (only &#x007E;0.02 V). Thus, the reduction of <inline-formula> <tex-math notation="LaTeX">${P}_{\text {s}}$ </tex-math></inline-formula> could improve endurance characteristics. On the contrary, it can also reduce the MW. Our work helps design the MFIS gate-stack to improve endurance characteristics.