A chip-stacked memory for on-chip SRAM-rich SoCs and processors

Abstract

Advanced SoC chips used in multimedia devices such as mobile phones have a number of dedicated functional IP cores, including 3D graphics and video codec, and require local memories with high bit density. Each IP core is connected to closely positioned local memories for fast access and wide bandwidth. The simultaneous operation of all of IP cores on a chip is an extremely rare situation and we anticipate that future integration of more IP cores onto a chip will increase the average number of sleeping IP cores at any given time. Therefore, current chip architectures that allocate local memories to individual IP cores will become increasingly inefficient in thier use of memory resources. In contrast to this, is the use of an off-chip external memory shared by a number of IP cores.