2008 · 23 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignIntegrated Circuit DesignInterconnect ArchitectureInterconnect DesignMixed-signal Integrated Circuit DesignProcessor Core DesignCmos ScalingLeakageLeakage PowerLeakage Power OptimizationLogical-to-physical Address MappingOn-chip InterconnectsSystem-on-chip ArchitectureVirtual Address Space
The paper presents a single-chip application and dual-mode baseband processor. It features triple V design - a technology in a low-power 65nm CMOS process that achieves 500MHz for two CPUsp; power domains are separated into 21 sub-blocks to reduce leakage power; introduces a new IP-MMU, which translates virtual address to physical address or physical address to physical address, to 17 different kinds of media IPs; and the interconnect buffer (ICB) extends its function to involve the IP-MMU.
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