EngineeringComputer EngineeringComputer ScienceComputer ArchitectureComputer-aided DesignDesign AutomationIntegrated Circuit DesignLayout DesignLayout EvaluationLayout OptimizationStandard Cell DesignVery-large-scale Integration LayoutArea OptimizationArea-efficient DesignFloorplanningIntegrated Circuit FloorplanningLayout EstimationLayout TechniquesStandard Cell PlacementVlsi Implementation
An efficient module area estimator for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for standard-cell and full-custom layout methodologies. The structure of the estimator and its algorithms are discussed. The authors' layout area estimates are very close to those of manually laid out modules.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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