Japanese Journal of Applied Physics · 2021 · 12 citations · 22 references
ComputingComputer EngineeringElectrical EngineeringComputer SecurityCryptographyMicroelectronicsCmos Circuit DesignCryptographic ArchitectureTamper DetectionTamper ResistanceAnti-tamper CircuitsAnti-tamper DesignCryptographic EngineeringHardware Overhead AnalysisInductor DesignIntegrated Circuit Tamper ResistancePhysical Tampering AttacksProof Of Concept Prototypes
Abstract This paper presents an inductive impulse self-destruction circuit utilized in a sense-and-react IC-level countermeasure against physical attacks on a cryptographic processor. Triggered upon an alarm signal assertion by an integrated attack sensor, the proposed circuit instantaneously generates >10 V high-voltage impulse to permanently destruct the cryptographic processor for enhancing tamper resiliency. A compact design with only a single on-chip inductor and a transistor significantly saves the hardware overhead. The inductor accumulates large electric energy in its magnetic field and the switch transistor suddenly opens the accumulated energy to boost the impulse voltage in an inertial manner. Since the inductor is drawn over the cryptographic core by existing on-chip IC interconnections, no extra area for the inductor and no any optional IC process steps are needed. This fully standard CMOS compatible, complete circuit solution, results in no fabrication cost penalty. A prototype implemented in both discrete components and a 0.18 μ m standard CMOS process successfully demonstrated the-proof-of-concept.
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Design principles for tamper-resistant smartcard processors
Oliver Kömmerling, Markus Kühn · 1999 · 543 citations