22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique

Abstract

Recent emerging applications, such as autonomous vehicles, artificial intelligence, and deep learning, require a large amount of data computation. The GDDR6 interface is a candidate solution because it can operate up to 64GB/s (16Gb/s/pin x 32 pins) with a lower cost than HBM. To communicate with GDDR6 DRAM [1], [2] the GDDR6 PHY requires high-speed signaling and, more importantly, read/write calibration for optimal margins. In this work, to transmit 18Gb/s data, while meeting the required GDDR6 I/O 1.35V supply, a thin-oxide high-voltage output driver [3] is used with a high-speed level shifter. A dual-mode equalizer is developed in the transmitter to selectively compensate for intersymbol interference (ISI) and far-end crosstalk (FEXT). For an accurate clock-phase calibration and a reduced optimal-reference-voltage search time a simultaneous calibration of clock phase and reference voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">REF</inf> ) is proposed in receiver. Multiphase gate training is proposed to create an internal source synchronous clock with finite cycles whose 1st rising edge is aligned to the 1st bit of read burst. Then, only valid 16b of a burst data are taken without a post processing.