IEEE Journal of Solid-State Circuits · 2018 · 32 citations · 23 references
EngineeringElectrical EngineeringDigital CommunicationLow-power DesignMicroelectronicsClock ManagementCmos Circuit DesignDynamic Power ReductionMixed-signal Integrated Circuit DesignModulationRadio-frequency Integrated CircuitsClock DistributionData Path DesignPhase-locked Loop DesignQuadrature Amplitude ModulationRf Cmos DesignTransmitter DesignTransmitter Front-ends
A transmitter implemented in 45-nm CMOS technology serializes data from 312.5 Mb/s to an 80-Gb/s pulse-amplitude modulation 4 output with no need for latches. Utilizing the charge-steering techniques and a frequency divider that directly generates quadrature outputs with a 25% duty cycle, the design consumes 21.7 mW in the data path and 22.3 mW in the phase-locked loop and clock distribution while delivering a swing of 630 mVpp with a 1-V supply.
23