A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture

Abstract

This paper presents a 4.1 megapixel, 280 frames/s, back-illuminated, stacked, global shutter (GS) CMOS image sensor with array-parallel analog-to-digital converter (ADC) architecture for region-control applications. The sensor solves an image distortion problem caused by rolling shutter in a pixel sub-array by utilizing a floating diffusion (FD) memory to implement GS operation. A newly developed circuit technique, the combination of active reset and frame correlated double sampling (CDS) operation, cancels Vth variation of pixel amplifier transistors as well as kTC noise. The active reset scheme suppresses output voltage variation of the pixel source follower. The chip supports 24-dB analog gain using a single-slope ADC and achieves 2.4e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> rms readout noise in the FD-memory-based GS. An intelligent sensor system with face detection derived from low-resolution images triggering high-resolution region-of-interest (ROI) output has been demonstrated with significantly reduced data bandwidth and low ADC power dissipation by utilizing the flexible area access function.