2.5D chip TSV open failure analysis by high resolution time-domain reflectometry

Abstract

2.5D chips with TSV and interposer are becoming the most popular packaging method with great increased flexibility and integrated functionality. However, great challenges have been posed in the failure analysis process to precisely locate the failure point of each interconnection in ultra-small size. The electro-optic sampling (EOS) based pulsed Time-domain reflectometry (TDR) is a powerful tool for the 2.5D/3D package diagnostics with greatly increased I/O speed and density. The timing of peaks in the reflected waveform accurately reveals the faulty location. In this work, 2.5D chip with known open failure location has been analyzed by a EOS based TDR system.