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A comparative study of strain and Ge content in Si<inf>1−x</inf>Ge<inf>x</inf> channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs
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Citations
1
References
2017
Year
Unknown Venue
Materials EngineeringSemiconductor TechnologyElectrical EngineeringEngineeringBuffer Layer FinfetsCrystalline DefectsPlanar PfetsTransistor Electrical PropertiesApplied PhysicsVirtual SubstrateSemiconductor Device FabricationMicroelectronicsPlanar FetsMechanics Of MaterialsGe ContentSemiconductor Device
Strained Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> channel pFinFETs and planar pFETs are fabricated on a strain relaxed buffer virtual substrate to comparatively study the electrical impact of strain and Ge content in the Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> channel. By comparing the transistor electrical properties of Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> pFETs on SRB with Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> pFETs on Si substrate, we successfully decouple the influence of strain and Ge content in the Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> channel on device performance such as gate stack quality, reliability, and carrier transport. Based on these understandings, dual channel Si/Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> FinFETs on the SRB with the optimized surface orientation is proposed to further improve the device performance.
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