A 0.67μm^2 self-aligned shallow trench isolation cell (SA-STI cell) for 3V-only 256Mbit NAND EEP-ROMs

Abstract

An ultra high-density NAND-structured memory cell, using a new Self-Aligned Shallow Trench Isolation(SA-ST1) technology, has been developed for a high performance and low bit cost 256Mbit Flash EEPROM. The SA-STI technology results in an extremely mall cell size of 0.67 um' per bit, 67% of the smallest Flash memory cell reported so far[ll. by using a 0.35~~ technology. The key technologies to realize a small cell size are (1) 0.4um width Shallow T rench Isolation (STI) to isolate neighboring bits and (2) a floating gate that is self-aligned with the STI, eliminating the floating-gate wings. Even though the floating-gate wings are eliminated, a high coupling ratio of 0.65 can be obtained by using the side-walls of the floating gate to increase the coupling ratio. Using this self-aligned structure, a reliable tunnel oxide can be obtained because the floating gate does not overlap the trench corners, so enhanced tunneling at the trench corner is ayoided. Therefore, the SA-STI cell combines a low bit cost with a high performance and a high reliability, such as the f ast programming (0.2usec/byte). fast erasing (2msec), good srite/erase endurance (>loa cycles), and excellent read disturb characteristics( >lO years). This paper describes the process technologies and the device performance of the SA-STI cell, which can be used to realize NAND EEPROYs of 256Mbit and beyond.