S. Shuto

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

H. Shiga, D. Takashima, S. Shiratake et al. · IEEE Journal of Solid-State Circuits · 2010 · 75 citations

Engineering, Computer Engineering, Electrical Engineering +17

PHASE STRUCTURE OF QCD-LIKE GAUGE THEORIES PLUS FOUR-FERMION INTERACTIONS

Kei-Ichi Kondo, S. Shuto, Koichi Yamawaki · Modern Physics Letters A · 1991 · 50 citations

Natural Sciences, Physics, Particle Physics +12

A 0.67μm^2 self-aligned shallow trench isolation cell (SA-STI cell) for 3V-only 256Mbit NAND EEP-ROMs

S. Aritome, S. Satoh, Toru Maruyama et al. · Medical Entomology and Zoology · 1994 · 26 citations

Engineering, Computer Engineering, Electrical Engineering +15

A 0.5-/spl mu/m, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor

Ryu Ogiwara, S. Tanaka, Y. Itoh et al. · IEEE Journal of Solid-State Circuits · 2000 · 24 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode

Katsuhiko Hoya, D. Takashima, S. Shiratake et al. · 2006 · 23 citations

Engineering, Computer Engineering, Electrical Engineering +12