Challenges and opportunities of vertical FET devices using 3D circuit design layouts

Abstract

We report on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer promising opportunities to enable further CMOS scaling and increased circuit layout efficiency. They allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values as compared to cells built with lateral GAA-NWFETs. Furthermore, vertical stacking of these devices also opens the path for SRAM 3D scaling, with a design presented here that can enable, with two levels of transistors in the vertical direction, to reduce by 39% the SRAM area per bit. The two vertically stacked VNWFETs are of the same doping type (n/n or p/p), and a lower complexity of implementation may be possible by taking advantage of the junctionless (JL) concept and its process simplicity, a topic also explored in this work.