Ratio based hot-carrier degradation modeling for aged timing simulation of millions of transistors digital circuits

Abstract

A ratio based hot-carrier degradation model for aged timing simulation of large CMOS circuits is presented. The model introduces gate-level representation and simply uses timing information. The proposed model is implemented in the prototype simulator in which the aged timing is obtained from the fresh timing and the precharacterized ratio. The simulated results show that the simulation can be performed at the size and speed of logic simulation with comparable accuracy of transistor-level simulator BTABERT.