Gate-Level Timing Simulation is a formal computational method within digital circuit analysis that models the propagation of signals through logic gates with precise timing delays derived from circuit netlists, distinguished by its focus on transistor-level timing accuracy before physical layout realization.
92
Publications
3.4K
Citations
264
Authors
93
Institutions
Publications per year
2017–2026
6
Parents
Publications
92
A gate-delay model for high-speed CMOS circuits
Florentin Dartu, Noel Menezes, Jessica Qian et al. · 1994 · 115 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17
1–5 of 92
Authors
264
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1–5 of 264
Institutions
93
University of California San Diego
San Diego, United States
9 h-index
21 publications
560 citations
Intel (United States)
Santa Clara, United States
6 h-index
19 publications
524 citations
University of California, Berkeley
Berkeley, United States
5 h-index
7 publications
151 citations
University of Illinois Urbana-Champaign
Urbana, United States
5 h-index
11 publications
666 citations
AT&T (United States)
Bedminster, United States
4 h-index
10 publications
222 citations
University of Stuttgart
Stuttgart, Germany
4 h-index
11 publications
230 citations
University of Southern California
Los Angeles, United States
4 h-index
12 publications
302 citations
Kyushu Institute of Technology
Kitakyushu, Japan
3 h-index
5 publications
104 citations
1–8 of 93
Venues
- Design Automation Conference
Conference · 4 publications · 82 citations
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- IEEE Journal of Solid-State Circuits
3 publications · 61 citations
3
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- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3 publications · 94 citations
3
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- IEEE Transactions on Applied Superconductivity
3 publications · 104 citations
3
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- IEEE Transactions on Computers
2 publications · 413 citations
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