Hungse Cha

A gate-level simulation environment for alpha-particle-induced transient faults

Hungse Cha, E.M. Rudnick, J.H. Patel et al. · IEEE Transactions on Computers · 1996 · 135 citations

Engineering, Vlsi Design, Mixed Analog +17

A logic-level model for α-particle hits in CMOS circuits

Hungse Cha, J.H. Patel · 2002 · 103 citations

Gate-level Simulators, Vlsi Design, Engineering +20

Fast timing simulation of transient faults in digital circuits

A. Dharchoudhury, Sung‐Mo Kang, Hungse Cha et al. · International Conference on Computer Aided Design · 1994 · 56 citations

Engineering, Computer Architecture, Transistor Level Simulation +18

A fast and accurate gate-level transient fault simulation environment

Hungse Cha, E.M. Rudnick, G.S. Choi et al. · 2002 · 45 citations

Engineering, Vlsi Design, Mixed Analog +16

Latch design for transient pulse tolerance

Hungse Cha, J.H. Patel · 2002 · 24 citations

Radiation Hardening, Engineering, Vlsi Design +20