A 0.4-μm/sup 2/ self-aligned contactless memory cell technology suitable for 256-Mbit flash memories

Masataka Kato, T. Adachi, Takeshi Tanaka, Akira Sato, Takashi Kobayashi, Y. Sudo, T. Morimoto, Haruki Kume, Takashi Nishida, K. Kimura

2002 · 12 citations · 0 references

Concepts

Abstract

This paper describes advanced self-aligned contactless memory-cell technology with sector erase and programming operations for a single power supply 256-Mbit flash memory. Using new self-aligned field-isolation technology and a deep punch-through stopper while minimizing the thermal budget of memory-cell fabrication process, 0.40-/spl mu/m/sup 2/ cells based on 0.25-/spl mu/m CMOS processes are fabricated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>