T. Adachi

Read-disturb degradation mechanism due to electron trapping in the tunnel oxide for low-voltage flash memories

Masataka Kato, Naoki Miyamoto, Haruki Kume et al. · 2002 · 81 citations

Engineering, Electrical Engineering, Materials Science +17

A flash-erase EEPROM cell with an asymmetric source and drain structure

Haruki Kume, H. Yamamoto, T. Adachi et al. · 1987 · 37 citations

Engineering, Computer Engineering, Electrical Engineering +14

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories

T. Kawahara, Takashi Kobayashi, Y. Jyouno et al. · IEEE Journal of Solid-State Circuits · 1996 · 32 citations

Engineering, Computer Engineering, Electrical Engineering +17

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

Hironori Fujisawa, M. Nakamura, Y. Takai et al. · IEEE Journal of Solid-State Circuits · 2005 · 12 citations

Engineering, Computer Engineering, Electrical Engineering +15

A 0.4-μm/sup 2/ self-aligned contactless memory cell technology suitable for 256-Mbit flash memories

Masataka Kato, T. Adachi, Takeshi Tanaka et al. · 2002 · 12 citations

Engineering, Computer Engineering, Electrical Engineering +16