Publication | Closed Access
Hot carrier reliability for 0.13 μm CMOS technology with dual gate oxide thickness
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2002
Year
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Electrical EngineeringSemiconductor DeviceEngineeringTotal Idsat DegradationNanoelectronicsStress-induced Leakage CurrentBias Temperature InstabilityApplied PhysicsTime-dependent Dielectric BreakdownHot Carrier ReliabilityμM Cmos TechnologyDevice ReliabilityMicroelectronicsBeyond CmosElectron TrappingNitrogen Affects NmosDual Gate
Different PMOS hot carrier degradation mechanisms are observed in a 0.13 /spl mu/m CMOS technology with ultra-thin gate oxide. Surprisingly, the gate voltage plays a significant role in total Idsat degradation, even at low temperature (40/spl deg/C). Hole trapping instead of electron trapping is observed under max Idsat degradation condition for PMOS. It is also shown that nitrogen affects NMOS and PMOS hot carrier degradation differently.