2016 · 35 citations · 5 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsMicroelectronicsSemiconductor DevicesChip PackagingIntegrated Circuit DesignIntegrated Circuit FabricationInterconnect TechnologySemiconductor Device MaterialsSemiconductor ReliabilityBarrier System DesignInterconnect FabricationInterconnect Reliability
A 36 nm pitch BEOL has been evaluated for the 7 nm technology node. EUV lithography was employed as a single-exposure patterning solution. For the first time, it is shown that excellent reliability results can be obtained for Cu interconnects at these small dimensions, by using a TaN/Ru barrier system and a selective Co cap.
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Interconnect performance and scaling strategy at 7 nm node
James Hsueh-Chung Chen, T. Standaert, Emre Alptekin et al. · 2014 · 45 citations
Engineering, Computer Engineering, Electrical Engineering +17