2015 · 19 citations · 12 references
EngineeringComputer EngineeringComputer ScienceComputer NetworksFault-tolerant SystemsInterconnection NetworksDesign For TestabilityFault DetectionInterconnect ArchitectureInterconnect DesignNetwork-on-chip DesignRoutingFault SimulationFault-tolerant NetworksHardware Fault ModelsInterconnect Fault AnalysisNetwork-on-chip ArchitecturesNetwork-on-chip Testability
Previous works on detecting and locating manufacturing faults-shorts, stuck-at, and open on an interswitch link of a channel in a network-on-chip (NoC) have been based on the assumption that these faults do not coexist. The works failed to diagnose all these faults when this assumption is relaxed. A deficiency for non-diagnosability of these faults is then represented. A packet address driven test strategy that detects and locates a faulty inters witch link in a NoC channel is proposed. The strategy addresses the intra-channel shorts, stuck at, and open faults coexist on inters witch links and is governed by parallel activation of diagonal routers. The strategy is scalable with mesh NoCs. Simulation results achieve 100% and more than 97% fault coverages when faults are diagnosed explicitly and implicitly respectively.
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A scalable test strategy for network-on-chip routers
Alexandre M. Amory, Eduardo Brião, Érika Cota et al. · 2006 · 103 citations