Modeling of single-event effects in circuit-hardened high-speed SiGe HBT logic

Abstract

This paper presents single-event effect (SEE) modeling results of circuit-hardened SiGe heterojunction bipolar transistor logic circuits. A simple equivalent circuit is proposed to model the ion-induced currents at all of the terminals, including the p-type substrate. The SEE sensitivity of a D-flip-flop was simulated using the proposed equivalent circuit. The simulation results are qualitatively consistent with earlier SEE testing results. The circuit upset is shown to be independent of the number of active paths. Considerable charge collection occurs through the reverse-biased n-collector/p-substrate junction, regardless of the status of the emitter steering current, resulting in circuit upset through the commonly connected load resistor. A heavily doped substrate is shown to be beneficial for SEE.