Journal of Computers · 2008 · 23 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesDynamic Power ReductionLow-power Digital Circuit DesignMemory Subsystem DesignPower ManagementSubthreshold Circuit DesignVoltage ScalingLow-power Memory ArchitectureLow-power Memory CircuitsLow-voltage Cmos DesignProcess Variation AnalysisProcess Variation RobustnessProcess Variation ToleranceUltra-low-power CmosUltra-low-voltage Circuit Design
Abstract—Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper presents a boosted word line voltage scheme, where an active body-biasing controlled boost transistor generates a pulsed word line voltage by capacitive coupling only when accessed. Simulation results have shown that the proposed approach not only shortens the access time but mitigates the impact of Vth variation on performance even at ultra low supply voltage less than
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Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda et al. · IEEE Journal of Solid-State Circuits · 2006 · 78 citations
Engineering, Computer Engineering, Electrical Engineering +17