Publication | Closed Access
The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes
159
Citations
11
References
1998
Year
EngineeringMechanical EngineeringChemical EngineeringPhysical Design (Electronics)Advanced Packaging (Semiconductors)Material ProcessingCorrosionIld Thickness VariationElectronic PackagingDielectric Thickness VariationSurface PolishingMaterials ScienceMaterials EngineeringElectrical EngineeringChip On BoardSurface TreatmentElectrical EffectsMicroelectronicsMetal-fill Patterning PracticesSurface ScienceMetallurgical ProcessSurface ProcessingMetal ProcessingOxide Chemical-mechanical Polishing
Oxide CMP suffers from layout‑dependent ILD thickness variation that degrades yield and performance, and metal‑fill patterning has been adopted to mitigate this issue. The authors propose a generalizable method to choose an optimal metal‑fill pattern that meets a target dielectric thickness variation while limiting added interconnect capacitance. The method evaluates grounded versus floating metal‑fill patterns, weighing their pros and cons, and applies criteria to minimize delay or crosstalk based on canonical metal‑fill structures. Experimental data show that metal‑fill reduces ILD thickness variation by 20 % and 60 % in two industrial cases, and a case study demonstrates an 82 % reduction, with pattern density identified as the key influencing factor.
In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation.
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