Active circuits under wire bonding I/O pads in 0.13 μm eight-level Cu metal, FSG low-k inter-metal dielectric CMOS technology

Abstract

Active circuits in terms of ring oscillator are moved to the place under the wire bonding pads in 0.13 μm full eight-level copper metal complementary metal-oxide-semiconductor process with fluorinated silicate glass low-k inter-metal dielectric. The bond pad with the 12 k/spl Aring/ thick aluminum metal film as a bonding mechanical stress buffer layer is deposited on the topmost copper metal layer. No noticeable degradations in gate delay or cycle time of ring oscillator are detected in a variety of test structures subjected to bonding mechanical stress and thermal cycling stress. This indicates that the underlying process technology may be reliable and manufacturable in placing active circuits under the bonding pads and thereby the die area utility is recovered fully. More evidence is created from transmission line pulsing experiments as well as capacitive-coupling experiments.