An implementation and analysis of a concurrent built-in self-test technique

Abstract

The authors propose a built-in concurrent self-test (BICST) technique for testing combinational logic circuits concurrently with their normal operation. They also introduce a concept of sharing the test hardware between identical circuits to reduce the overall area overhead. They implemented this technique in the design of an ALU (arithmetic logic unit) with online test capability in CMOS technology. The additional hardware used for a 12-bit ALU was 19% of the total chip area, and it did not impose any timing overhead on the operation of the ALU. The overhead decreases with an increase in the size of the ALU. The authors define some measures for evaluating the performance of the BICST technique and discuss methods for their computation and include both simulation and analytical results. In addition to detecting permanent faults, the BICST technique can also be used for detecting intermittent and transient faults. The authors propose some methods for detecting intermittent faults and for computing the transient fault coverage.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>