A 5K-gate bipolar masterslice LSI with a 500 ps loaded gate delay

Abstract

A fully ECL-compatible 5K-gate bipolar subnanosecond masterslice has been developed for use in computer and communication systems. A new circuit design and a 1.5-/spl mu/m rule oxide isolation process employing three-level metallization have made possible a high performance of 0.32 pJ/gate and a small cell size of 3937.5 /spl mu/m/SUP 2/. An alterable configuration cell (ACC) circuit based on nonthreshold logic (NTL) is adopted as the basic internal cell. The masterslice has been applied to a dual 36-bit ALU consisting of 3486 cells. An unloaded gate delay of 320 ps and a loaded gate delay of 500 ps with a power dissipation of 1 mW/gate were obtained with a 15-stage ring oscillator and a 10-stage path delay in the 36-bit ALU.