A MESFET Variable-Capacitance Model for GaAs Integrated Circuit Simulation

T. Takada, Yokoyama, Kiyoyuki, +2

IEEE Transactions on Microwave Theory and Techniques

Device ModelingElectrical EngineeringMesfet Variable-capacitance ModelEngineeringPhysical Design (Electronics) +13

A three-dimensional analysis of semiconductor devices

A. Yoshii, H. Kitazawa, M. Tomizawa, +2

IEEE Transactions on Electron Devices

Numerical AnalysisEngineeringPower ElectronicsSemiconductor DeviceSemiconductors +16

Two-dimensional semiconductor analysis using finite-element method

T. Adachi, A. Yoshii, T. Sudo

IEEE Transactions on Electron Devices

EngineeringCommon EmitterPower ElectronicsSemiconductor DeviceSemiconductors +14

An LSI adaptive array processor

Toshiki Kondo, T. Nakashima, Masanao Aoki, +1

IEEE Journal of Solid-State Circuits

System On ChipElectrical EngineeringAap LsiEngineeringVlsi Design +12

A numerical analysis of a heterostructure InP/InGaAs photodiode

K. Yokoyama, M. Tomizawa, H. Kanbe, +1

IEEE Transactions on Electron Devices

Numerical AnalysisWide-bandgap SemiconductorEngineeringOptoelectronic DevicesPhotoelectric Sensor +14

Threshold-voltage analysis of short- and narrow-channel MOSFET's by three-dimensional computer simulation

R. Kasai, K. Yokoyama, A. Yoshii, +1

IEEE Transactions on Electron Devices

EngineeringSmall Size MosfetThree-dimensional Computer SimulationSmall Size EffectsSemiconductor Device +14

CAD systems for VLSI in Japan

T. Sudo, Tomoaki Ohtsuki, Satoshi Goto

Proceedings of the IEEE

Industrial DesignPhysical Design (Electronics)EngineeringElectronic Design AutomationAdvanced Design +12

Analysis of High-Speed GaAs Source-Coupled FET Logic Circuits

M. Idda, T. Takada, T. Sudo

IEEE Transactions on Microwave Theory and Techniques

Hardware SecurityLow-power ElectronicsElectrical EngineeringScfl CircuitEngineering +12

Semiconductor device simulation at NTT

K. Yokoyama, M. Tomizawa, A. Yoshii, +1

IEEE Transactions on Electron Devices

EngineeringSimulationSemiconductor DeviceSemiconductorsNanoelectronics +14

A 5K-gate bipolar masterslice LSI with a 500 ps loaded gate delay

Masao Suzuki, S. Horiguchi, T. Sudo

IEEE Journal of Solid-State Circuits

Hardware SecurityLow-power ElectronicsElectrical EngineeringEngineeringVlsi Design +11